The AES-P IP core from Alma Technologies implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key. The Block Cipher mode of operation is run-time programmable to ECB, CBC, CFB, OFB, or CTR. The AES-P core is available in two variations, the standard AES32-P and the fast AES128-P.

AES32-P has a 32-bit internal datapath, while the AES128-P uses 128-bit datapath. The AES32-P is more compact in size, but offers a lower throughput than the AES128-P. The AES32-P needs 44/52/60 clock cycles to encrypt or decrypt an input block using 128/192/256-bit cipher-key, respectively, while only 11/13/15 clock cycles are required for the same by the AES128-P core.

During each step of the encryption or decryption processing the core requires a previously calculated Round Key Value, derived from the cipher-key using a key expansion algorithm. The Round Key Values must be stored to the internal Round Key Table, from which the core retrieves the appropriate one for each processing step. Alternatively, instead of directly programming the Round Key Values to the Round Key Table, an optional Key Expander module can be provided. This module automatically calculates the Round Key Values and fills the internal Round Key Table according to the cipher-key given to the core.

The AES-P core is equipped with easy-to-use fully stallable interfaces for both input and output. These are designed to permit the user application to pause the produced output data stream when it is not able to receive data, or to pause the input stream towards the core according to data arrival rate.

IP Deliverables

Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license

Self-checking testbench environment sources, including sample BAM generated test cases

Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

Symbol

Features

Compliant, High-Performance and Standalone Operation

Fully compliant to the Advanced Encryption Standard (AES) (FIPS PUB 197)

Run-time programmable encrypt or decrypt

Run-time programmable Block Cipher mode: ECB, CBC, CFB, OFB, CTR

Run-time programmable cipher-key size: 128-, 192-, 256-bit

Includes Round Key Table for storage of Round Key values

Optional Key Expansion module for automatic generation of the Round Key values

AES32-P: Processes each 128-bit block in 44/52/60 clock cycles for 128/192/256-bit cipher-key respectively

AES128-P: Processes each 128-bit block in 11/13/15 clock cycles for 128/192/256-bit cipher-key respectively

High-speed, flow controllable, streaming I/O data interfaces

Trouble-Free Technology Map and Implementation

Fully portable, self-contained RTL source code

Strictly positive edge triggered design

D-type only Flip-Flops

Fully synchronous operation

No special timing constraints required

No false paths

No multi-cycle paths

Literature

Request a Quote for the AES-P  IP core

If you have an account with us, please login bellow to retrieve your contact information automatically:

LOGIN

LOGIN

Email:

Password:

Incorrect Login!

OR

Manually fill in your contact information.
Completing fields in bold is required. Please use your business email.

CONTACT INFORMATION

CONTACT INFORMATION

Name:

Business Title:

Business Email:

Company Name:

Company Website:

Telephone:

Country:

AES-P IP CORE LICENSING OPTIONS

AES-P IP CORE LICENSING OPTIONS

License Type:

FPGA Vendor:

Additional Information
and/or
Technical Requirements:

ASICFPGAAMD-XilinxEfinixIntelLatticeMicrochip--- Enter Optional Text ---