H264-BP-E
Baseline Profile H.264 Encoder
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The H264-BP-E core from Alma Technologies is an advanced self-contained hardware H.264 encoder that conforms to the ITU-T H.264 Constrained Baseline Profile. This core is available in Intra-only [IDR], Light Motion Estimation [LME] and Full Motion Estimation [FME] prediction engine configurations. It supports the real time encoding of both single and multiple 8-bit 4:2:0 video streams, up to Profile Level 5.2. The H264-BP-E is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.
The encoder accepts the uncompressed video data in planar, interleaved, or macroblock scan format. It outputs standalone, standard compliant, Annex B NAL byte stream. No post processing on the output stream, other than (for example) stroring, muxing or transmitting, is required. The output NAL byte stream can be decoded, as is, by any ITU-T H.264 compliant decoder that satisfies the Level requirements of the stream and conforms to the Constrained Baseline, or higher, ITU-T H.264 Profile.
The H264-BP-E requires minimal host intervention as it only needs to be programmed once per video sequence. Once programmed, it can encode an arbitrary number of video frames without needing any CPU, GPU, or other type of support by the host system.
The H264-BP-E core implements a simple and flexible, requests based, external memory interface with independent read and write data paths. This makes the H264-BP-E independent of memory type, supporting for example operation with SRAM or SDR and DDRx SDRAM types of memory. The encoder is designed to be tolerant to memory delays and latencies, which may be present on shared memory system architectures.
The H264-BP-E core is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the H264-BP-E is a reliable and easy-to-use and integrate IP.
IP Deliverables
Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license
Self-checking testbench environment sources, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
