SHA1
SHA-1 IP Core Secure Hash Function
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The
The core is composed of two main units, the SHA1 Engine and the Padding Unit
as shown in the block diagram. The SHA1 Engine applies the
SHA1 loops on a single 512-bit message block, while the Padding Unit splits the input message into
512-bit blocks and performs the message padding on the last block of the message.
The processing of one 512-bit block is performed in 82 clock cycles and the bit-rate
achieved is 6.24Mbps / MHz on the input of the SHA1 core.
The SHA1 core is equipped with easy to use fully stallable interfaces both for input and output. These are designed to permit the user's application to stop the data stream from the core when it is not able to receive data or to stop the input stream towards the core according to data arrival rate.
IP Deliverables
Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license
Self-checking testbench environment sources, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
Symbol
Features
Compliant to FIPS 180-1 specification of SHA-1.
Bit padding internally implemented.
Supports 2^64-1 bits maximum message length.
Supports input message length multiple of 8-bit.
Initial value of the chaining variables selected before synthesis.
82 processing cycles per 512-bit message block.
Fully stallable input and output interfaces, ideal for streaming applications.
Designed for Easy Integration
Optimum design for ASIC or FPGA implementations.
Comprehensive documentation and a complete verification environment, including a bit-accurate model.